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Все сайты магазина грузятся без рекламы. WebMoney не будет размещаться на этом сайте.1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Background Art
A contact between an upper wiring and a lower wiring formed on different layers is a key point of an attempt to achieve a high-speed operation. With an increasing microfabrication of a semiconductor device, a contact resistance, i.e., a resistance between a conductive film (for example, aluminum (Al)) to be a lower wiring and an upper wiring, increases. Therefore, a technology of directly contacting an Al film or the like to be the upper wiring with a pad of a low-resistance metal such as tungsten (W) is currently researched (see, for example, Japanese Patent Laying-Open No. 2004-332046).
The technology described in Japanese Patent Laying-Open No. 2004-332046 will be described below. FIGS. 11A to 11D and FIGS. 12A to 12D are diagrams for explaining a method of manufacturing a semiconductor device. FIGS. 11A to 11D are diagrammatic sectional views illustrating a conventional manufacturing method. FIGS. 12A to 12D are diagrams illustrating steps of the conventional manufacturing method.
In a conventional method of manufacturing a semiconductor device, first as illustrated in FIG. 11A, a field insulation film 805 is formed on a silicon substrate 802. Then, a gate insulation film 806 is formed on the silicon substrate 802.
Next, as illustrated in FIG. 11B, a gate electrode 807 is formed on the gate insulation film 806. Next, an interlayer insulation film 808 is formed on the gate insulation film 806, the gate electrode 807, and the silicon substrate 802.
Next, as illustrated in FIG. 11C, a resist pattern 809 is formed on the interlayer insulation film 808. The interlayer insulation film 808 and the gate insulation film 806 are etched using the resist pattern 809 as a mask, and thereby contact holes 810 and

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